The present invention is directed to semiconductor devices and, more specifically, to semiconductor devices including thyristor-based devices.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-die microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices has led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the circuit design, construction, and manufacture of semiconductor devices concerns circuitry such as semiconductor memories and other circuitry used to store digital information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information.
There are a number of semiconductor memories in wide spread use. Two such semiconductor memories are SRAM and DRAM. DRAM is very common due to its high density (e.g., high density has benefits including low price). DRAM cell size is typically between 6 and 8 F2, where F is the minimum feature size. However, DRAM is relatively slow compared to microprocessor speeds (typical DRAM access times are xcx9c50 nSec) and requires refresh. SRAM is another common semiconductor memory. SRAM is much faster than DRAM (SRAM access times can be less than or equal to about 5 nSec) and do not require refresh. SRAM cells are typically made using 4 transistors and 2 resistors or 6 transistors, which results in much lower density and is typically about 60-100 F2.
A novel type of NDR-based SRAM has been recently introduced that can potentially provide the speed of conventional SRAM at the density of DRAM in a CMOS compatible process. This new SRAM cell uses a thin capacitively-coupled NDR device and more specifically a thin capacitively-coupled thyristor to form a bistable element for the SRAM cell. For more information about this type of NDR device, reference may be made to: xe2x80x9cA Novel Thigh Density, Low Voltage SRAM Cell With A Vertical NDR Device,xe2x80x9d VLSI Technology Technical Digest, June, 1998; xe2x80x9cA Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-Scale Memories,xe2x80x9d International Electron Device Meeting Technical Digest 1999, and xe2x80x9cA Semiconductor Capacitively-Coupled NDR Device And Its Applications For High-Speed High-Density Memories And Power Switches,xe2x80x9d PCT Int""l Publication No. WO 99/63598, corresponding to U.S. patent application Ser. No. 09/092,449, now U.S. Pat. No. 6,229,161 issued May 18, 2001.
While the thin-capacitively-coupled-thyristor type device is effective in overcoming many previously unresolved problems for memory applications, an important consideration is designing the body of the thyristor sufficiently thin so that the capacitive coupling between the control port and the underlying thyristor base region can substantially modulate the potential of this base region and result in an outflow of this base region""s minority carriers (versus MOSFET operation where channel inversion results from an inflow of minority carriers).
The above-mentioned and other difficulties associated with the formation of vertical thyristor-based devices present challenges to the manufacture and implementation of such devices.
The present invention is directed to overcoming the above-mentioned challenges and others related to thyristor-based memory devices, such as the devices discussed above. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
One aspect of the present invention is directed to a semiconductor device including a thyristor designed to reduce or eliminate manufacturing and operational difficulties commonly experienced in the formation and operation of NDR devices. According to one example embodiment, the semiconductor substrate is trenched adjacent a doped or dopable substrate region, which is formed to included at least two vertically-adjacent thyristor regions of different polarity. A capacitively-coupled control port for the thyristor is coupled to at least one of the thyristor regions. The trench also includes a dielectric material for electrically insulating the vertically-adjacent thyristor regions.
In a more particular example embodiment of the present invention, the thyristor is a thin capacitively coupled thyristor as characterized previously. The thin-capactively-coupled-thyristor-type device includes at least two contiguously adjacent portions of opposite doping and is electrically isolated from other circuitry in the device by the trench. A control port is capacitively coupled to one or more of the contiguously adjacent portions, and in one particular implementation, is formed in the trench. The control port can be further isolated from selected regions of the thyristor via an insulative material formed in the trench, and in one implementation the trench includes an oxide spacer at a bottom portion of the trench.
Other aspects of the present invention are directed to the location of the control port. In a more specific approach, the above example embodiment further involves forming the control port in the trench so that the control port is capacitively coupled to at least one of the vertically-adjacent regions. In one implementation, the control port is capacitively coupled to only one of the vertically-adjacent regions and is adapted to control the operation of the thyristor.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. Other aspects include methods for using and for manufacturing such a thyristor and to memory arrangements employing the above-characterized thyristor construction. The figures and detailed description that follow more particularly exemplify these embodiments.